Aryabartta Sahu
Ph.D. Scholar,
Dept. of Computer
Science & Engg., Indian Institute of
Technology Delhi
Office:
Architecture Lab, Room No- IIA/505, 4th Floor,
Bharti Buliding, IIT
Delhi,
Email: asahu
AT
cse.iitd.ernet.in Phone:
+91-11-2659-6041
Residence:
NC-28, Zhanskar Hostel,
IIT Delhi, Hauz
Khas, New Delhi-16, India.
My new web link http://www.iitg.ernet.in/asahu/
Research:
Topic
: Evaluation and Mapping of
Applications on Heterogeneous Multiprocessor
Supervisors
: M.
Balakrishnan and P. R.
Panda
Publications:
1.
A Generic Platform for
Estimation of
Multi-threaded Program Performance on Heterogeneous
Multiprocessor
A. Sahu, M. balakrishnan, Preeti Ranjan
Panda, To apear in IEEE/ACM SIGDA Design
Automation
and Test
in Europe
(DATE) Nice, France,
April 2009.
Teaching Assistant:
Involved in other
work:
1. Platform based
design of real time
sonar
beam-former
2.
Design of multiprocessors simulator using
simple-scalar
3.
Design space exploration of low power LDPC codecs
4.
Generic profiler using
SUIF compiler framework
5. Cache
behavior inclusion in perf estimator using
Valgrind
6.
Perf. estimation of SPEC Benchmark
7. Cell
Simulator and Its performance estimation
8.
Multiprocessor
cache sharing policy
Resume:
AryabarttaSahu.Resume.jpg
Tutorial:
IITD
Internal link
Tutorials
Help text for compilation & run
(Pthread, OpenMP, MPI, Cilk, StremIt, Gcov, Gprof, valgrind, simplescalar, Latex)