About Me
Thanks for visiting my webpage. I have now joined IIT Hyderabad and my new webpage is located at this link.
I am working as a project scientist with Prof. Preeti Ranjan Panda in the Khosla School of IT. I am a part of the Memory and embedded Architecture Research Group (MARG).
I completed my Ph.D. from the Department of Computer Science and Engineering of IIT Delhi in October 2020. My thesis is titled "A Framework For Designing Context-Aware Adaptive Embedded Systems" advised by Prof. M. Balakrishnan and Prof. Kolin Paul. I was a recipient of Visvesvaraya Ph.D. fellowship supported by MeitY (Ministry of Electronics and Information Technology, Government of India).I worked at Texas Instruments India Pvt. Ltd. in Bangalore for 8+ years in various SoC design activities - design for testability, verification, specification, and firmware development.
Research
Research summary
My Ph.D. thesis is titled "A Framework For Designing Context-Aware Adaptive Embedded Systems". The thesis proposes improvements in the design flow for emerging embedded systems executing ML and AI workloads. A short summary of the work can be found at link. I also wrote the summary of my Ph.D. work in the form of a story.
I am also involved in exploring thermal management strategies for 3D memories jointly with Lokesh Siddhu. Jointly with Divya Praneetha, I am investigating optimization opportunities when using Negative Capacitance FET (NCFET) based caches in processor systems.
Publications
- Lokesh Siddhu, Rajesh Kedia, and Preeti Ranjan Panda. "CoreMemDTM: Integrated Processor Core and 3D Memory Dynamic Thermal Management for Improved Performance". In Design Automation and Test in Europe (DATE) 2022. Accepted.
- Divya Praneetha Ravipati, Rajesh Kedia, Victor M. van Santen, Joerg Henkel, Preeti Ranjan Panda, and Hussam Amrouch. "FN-CACTI: Advanced CACTI for FinFET and NC-FinFET Technologies". In IEEE Transactions on Very Large Scale Integration Systems (TVLSI). Accepted. [Link to paper]
- Shikha Goel, Rajesh Kedia, Rijurekha Sen and M. Balakrishnan. "INFER: INterFerence-aware Estimation of Runtime for Concurrent CNN Execution on DPUs". In International Conference on Field Programmable Technology (FPT), 2020. [Link to paper] [Download preprint]
- Lokesh Siddhu, Rajesh Kedia, and Preeti Ranjan Panda. "Leakage Aware Dynamic Thermal Management of 3D Memories". In ACM Transactions on Design Automation of Electronic Systems (TODAES), October 2020. [Link to paper]
- Rajesh Kedia, Shikha Goel, M. Balakrishnan, Kolin Paul, and Rijurekha Sen. "Design Space Exploration of FPGA Based System with Multiple DNN Accelerators". In IEEE Embedded Systems Letters (ESL), Accepted. [Link to paper] [Download preprint][A 4-min. short video]
- Rajesh Kedia, M. Balakrishnan, and Kolin Paul. "Work-in-Progress: A case for design space exploration of context-aware adaptive embedded systems". In CODES+ISSS, Oct. 2019. [Link to paper]
- Rajesh Kedia, M. Balakrishnan, and Kolin Paul. "GRanDE: Graphical representation and design space exploration of embedded systems". In Euromicro conference on Digital Systems Design (DSD), Aug. 2019. [Link to paper]
- Rajesh Kedia, Anupam Sobti, Mukund Rungta, Sarvesh Chandoliya, Akhil Soni, Anil Kumar Meena, Chrystle Myrna Lobo, Richa Verma, M. Balakrishnan and Chetan Arora. "MAVI: Mobility Assistant for Visually Impaired with Optional Use of Local and Cloud Resources". In 32nd International Conference on VLSI Design (VLSID), Jan. 2019. [Link to paper]
- Rajesh Kedia, Yoosuf K K, Pappireddy Dedeepya, Munib Fazal, Chetan Arora, and M. Balakrishnan. "MAVI: An embedded device to assist mobility of visually impaired". In 30th International Conference on VLSI Design (VLSID), Jan. 2017. [Link to paper]
Open source releases
- CoMeT (Co and Memory Thermal Simulator): A first-ever integrated tool for thermal simulation of core and memory in a computing systemi, built over Sniper architecture simulator. Supports various integration of core and memory like 2D, 2.5D, and 3D. Many other useful features are also included. [Link to repository]
- Visualization tool: This is a generic visualization tool to plot graphs for data present in csv format and can be used by researchers to plot various kind of graphs to be included in reports/presentations/documents. Specific to my research, we have included some capabilities needed for efficiently performing Design Space Exploration. [Link to repository]
Technical Service
- Reviewer for leading conferences and journals like ASPDAC, DAC, IEEE ESL, CODES+ISSS, IEEE TCAD, ACM TECS
Suggested reading
This list contains selected research papers that I found worth sharing. [link]MAVI
Mobility Assistant for Visually Impaired
I have been involved in MAVI from July 2015 till June 2019 as a mentor for UG/PG students and also planning out various activities and scope for this project. MAVI has been one of the case studies for my Ph.D. thesis.
Academics
Current CGPA = 9.74/10.0
Coursework at IITD:
| Sl. No. | Course Name | Instructor | Session |
|---|---|---|---|
| 11 | Theory of Computation | Naveen Garg | Spring, 2016-17 |
| 10 | Low Power Computing | Sorav Bansal | Fall, 2016-17 |
| 9 | Intelligent Information Processing | Multiple Instructors | Spring, 2015-16 |
| 8 | System Level Design and Modeling | M. Balakrishnan | Fall, 2015-16 |
| 7 | Advanced Data Structures | S. N. Maheswari | Fall, 2015-16 |
| 6 | Compiler Optimizations | Preeti R. Panda | Fall, 2015-16 |
| 5 | Communication Skills | Akash Raha | Fall, 2015-16 |
| 4 | Operating Systems | Sorav Bansal | Spring, 2014-15 |
| 3 | Architecture of High Performance Computers | Anshul Kumar | Spring, 2014-15 |
| 2 | Embedded Computing | Kolin Paul | Spring, 2014-15 |
| 1 | Low Power System Design Techniques | M. Balakrishnan | Spring, 2014-15 |
Course projects:
- Compiler Optimizations: Effective Last Level Cache (LLC) partitioning using static dynamic analysis (Use of compiler hints to aid cache partitioning for run time system).
- System Level Design and Modeling: Power Performance tradeoff analysis for High level synthesis of Matrix multiplier. [slides]
- Low Power Computing: Analysis and comparison of performance, power and energy for various workloads on different class of systems (laptop, desktop and server) using hardware counters. [Report]
- Advanced Data Structures: Implementation of Fibonacci heap and using it to implement Fredman Tarjan MST algorithm. Analysis and comparison of performance with standard Prim's algorithm. [Design doc] [Report]
- Architecture of High Performance Computers: Implementation of Tomasulo's out-of-order pipeline (with ROB) in an in-house architecture simulator (Tejas).
- Embedded Computing: Interfacing various sensors (Accel, Gyro, motion and proximity) to Intel Galileo board.
- Intelligent Information Processing: Analysis of Back Propagation Neural Network accuracy (by varying different parameters) for classification of Iris flowers. [Report]
Academics prior to IITD:
| Degree | Details | Year | Score |
|---|---|---|---|
| B.Tech. In ECE | MNIT Jaipur | 2002-2006 | 9.71/10 |
| XII | CHSE Orissa | 2000-2002 | 83% |
| X | CBSE | 2000 | 89% |
Work Experience
Teaching Assistant (TA) Duties at IITD:
| Sl. No. | Course Name | Instructor | Session |
|---|---|---|---|
| 9 | Synthesis of Digital Systems (also running as MOOC on NPTEL) | Preeti Ranjan Panda | Fall, 2019-20 |
| 8 | Design of Cyber Physical Systems (GIAN course) | Peter Marwedel (TU Dortmund) | Feb.12-Feb.20 2018 |
| 7 | Embedded Systems Design | M. Balakrishnan | Spring, 2017-18 |
| 6 | Digital Logic and System Design | Anshul Kumar | Fall, 2017-18 |
| 5 | Computer Architecture | Anshul Kumar | Spring, 2016-17 |
| 4 | Embedded Computing | Kolin Paul | Fall, 2016-17 |
| 3 | Operating Systems | Kolin Paul | Spring, 2015-16 |
| 2 | System Level Design and Modeling | M. Balakrishnan | Fall, 2015-16 |
| 1 | Big Data and Cloud Computing | Karuna P. Joshi | Spring, 2014-15 |
Key contributions during TA work:
- My primary contributions during TA work has been significant involvement in definition of lab exercises (System level design and modeling, Operating systems, Embedded computing, Computer architecture, and Digital logic and system design).
- Another important contribution is towards defining and implementing automated evaluation system using Moodle VPL. We have deployed this infrastructure for automated evaluation for courses (Operating systems, VHDL based digital system design) where automation was deemed very difficult. Overall, it has led to easing work for TAs and bring in uniformity, while improving students' experience of assignment submission.
- In all my TA work, the focus has been on methods to ensure objectivity of evaluation, and provide timely feedback to the students.
- Recommended as "Outstanding TA" thrice and honourable mention once during 3 years.
Mentoring student projects:
I have been involved in many different student projects (UG and PG) as a mentor. The list is captured here.Industry Experience:
| Organization | Period | Summary of work |
|---|---|---|
| Texas Instruments India Pvt. Ltd. | Jul 2006 - Dec 2014 | Worked as a part of Microcontroller (MCU) design team: Design for Test (DfT), Functional Verification, Architecture Definition. |
Other responsibilities (volunteering)
- Co-ordinated volunteer activities and contributed to planning and organization of VLSID 2019 held at New Delhi (jointly with Lokesh Siddhu). Some of the notable involvements include:
- Mobile app for the conference - Defining the specifications for the app, discussing with the vendor, and planning the usage of the app for the conference. The mobile app was a big hit among the attendees and marked the beginning of going digital for VLSID
- Identifying means of improving the experience of attendees and discussing with the corresponding chairs
- Handling the backend for fellowship application process
- Publicity through facebook (social media)
- Being the interface between attendees, volunteers, event managers, and the chairs for a large conference like VLSID
- Ph.D. student representative for CSE department (from Nov. 2016 till July 2017): coordinating events, communicate general concerns to higher authorities,
areas to enable better experience for Ph.D. students, etc. Some notable contributions of the team are:
- Organized annual PhD Symposium of IITD CSE/SIT departments in Dec. 2016.
- Website rollout dedicated to our Ph.D. program.
- Moving to a moodle based online entrance test from a paper based test - enabling a better experience for candidates and faculty in the admission process.
- Conceptualized and enabled walk-in option for Ph.D. entrance test - providing opportunity to candidates who missed the application deadline.
- Member of the FUNACE team at TI for 2 years: coordinating fun events within the team, plan and enable better team building, etc.
Others/ External Links
Preparing for Ph.D. interviews
My travel experiences and conference visits
My wiki article on Bus Encoding
Contact Details
Email: rkedia@cse.iitd.ac.in
Office:
Room 301, Research Scholar Room-A,
SIT Building, IIT Delhi,
Hauz Khas, New Delhi - 110016.
Credits
Template borrowed from Styleshout
